1. Field
The present invention relates to a method of shield line placement for use in the design of a semiconductor integrated circuit, and to a design apparatus and design program for designing a semiconductor integrated circuit by automatically placing the shield lines.
2. Description of the Related Art
In recent years, as feature sizes for large-scale integrated circuits (LSIs) continue to decrease and packing density increase, crosstalk noise between wiring lines has come to present a non-negligible effect on the wiring lines. To prevent such crosstalk noise, the prior art has employed a circuit design that provides shielding by placing ground nets or power supply nets on both sides of signal nets (for example, clock nets) that can cause interference with other signal nets because of transmission of high-frequency signals or signal nets that need protection against interference from other signal nets (for example, refer to Japanese Unexamined Patent Publication No. 2000-259695).
As disclosed in Japanese Unexamined Patent Publication No. 2000-259695, shield line routing is partly automated in semiconductor integrated circuit design. However, in actual design work for high-end LSIs such as state-of-the-art, high-performance processors, the reality is that not only the routing of signal lines but also the routing of shield lines for shielding the signal lines is determined by humans, and the routing paths for these signal lines and shield lines are manually entered using a CAD application for semiconductor integrated circuit design. Accordingly, the prior art has had the following problems.
In the prior art CAD application for a semiconductor integrated circuit design, etc., signal lines and their associated shield lines have been handled as separate, independent routing data. Accordingly, if there arise a need, for design reasons, etc., to change the placement of the signal lines after the signal lines and the shield lines have once been routed, the routing of the shield lines has had to be changed manually so as to match the changed routing of the signal lines. In the prior art, therefore, there has been a concern that the operator may inadvertently forget to edit the shield lines that should be edited at the same time.
There has also been a concern that the operator may mistakenly edit shield lines that have no relevance to the edited signal lines. This problem has also occurred because the routing data of the signal lines and that of the shield lines have been handled as separate, independent data.
Especially, in the case of high-end LSIs, since fine adjustments need to be made after the routing is once done, the above problems associated with the editing performed after the routing add to the complexity of design work and pose serious difficulties.
In the prior art design flow, after determining the routing of the signal lines, the routing of their associated shield lines is determined, as described above. This has given a rise to the possibility that a signal line may be routed in such a manner that the associated shield line cannot be placed for it. If the associated shield line cannot be placed, proper shielding cannot be provided for the signal line; therefore, in this case, the routing of the signal line has to be redone from the beginning, which greatly affects the efficiency of the routing work.
If there occurs a change in design rule after the shield lines have been placed, and the need arises to apply the same change to a plurality of shield lines, each individual one of the plurality of shield lines has had to be corrected by hand, and hence the problem that the work efficiency is low.
An embodiment of the present invention has been devised in view of the above problems, and one of an object of the embodiment is to increase the efficiency of semiconductor integrated circuit design work by greatly saving the labor required for the routing of shield lines in the circuit design of a semiconductor integrated circuit in which the placement of signal lines and shield lines is determined by humans.